Evaluating pattern for measuring an erosion of a semiconductor wafer polished by a chemical mechanical polishing

ABSTRACT

An evaluating pattern is comprised of a conductive pattern which has a rectangular configuration, an insulating layer which is formed on the conductive pattern, and a conductive material filled into contact holes which is formed in the insulating layer on the middle of the conductive pattern.

[0001] The present application claims priority under 35 U.S.C. § 119 toJapanese Application No. 2000-288451, filed on Sep. 22, 2000, which ishereby incorporated by reference in its entirely for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to an evaluating pattern formeasuring an erosion of a semiconductor wafer polished by a chemicalmechanical polishing method.

[0004] Description of the Related Art

[0005] A chemical mechanical polishing method (CMP method) has bees usedfor forming a semiconductor device. As normally, a plurality ofsemiconductor devices are simultaneously formed on a semiconductorwafer, such CMP method is applied for the semiconductor wafer.

[0006] In the case where the CMP method is applied for a damacineprocess, occurrence of an erosion in a densely region where many contactholes or conductive lines are thicken in an narrow distance. The erosionis that a thickness of an insulating region in the densely regionbecomes thin by the CMP method, compared with a predetermined thickness.The reason is reported that a speed of polishing the insulating layerbecomes faster in the densely region.

[0007] If the thickness of the insulating layer becomes thinner beyond apermissible range by the erosion, it is possible that an insulation isbroken or a current leak occurs in the semiconductor device.

[0008] The semiconductor wafer which includes such semiconductor devicehaving such excessive erosion is evaluated as a defective product bymeasuring the thickness of the insulating layer. A contact type measurefor measuring bumps occurred by the erosion is used for suchmeasurement.

[0009] As the contact type measure directly contacts with elements inthe semiconductor device, it is possible to damage the elements. As aresult, such damage may decline a yield of the semiconductor device.

SUMMARY OF THE INVENTION

[0010] An object of the present invention is to provide an evaluatingpattern for measuring an erosion of a semiconductor wafer polished by achemical mechanical polishing method.

[0011] To achieve the object, an evaluating pattern of one typicalinvention is comprised of a conductive pattern which has a rectangularconfiguration, an insulating layer which is formed on the conductivepattern, and a conductive material filled into contact holes which isformed in the insulating layer on the middle of the conductive pattern.

[0012] According to the present invention, it is easy to recognize theevaluation pattern on a semiconductor wafer. As a measuring point isarranged in the middle of the rectangular conductive pattern, it isfacile to identify the measuring point. That is, the measuring point inthe middle of the rectangular conductive pattern is easily identified byrecognizing sides of the rectangular conductive pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] While the specification concludes with claims particularlypointing out and distinctly claiming the subject matter which isregarded as the invention, it is believed that the invention, theobjects and features of the invention and further objects, features andadvantages thereof will be better understood from the followingdescription taken in connection with the accompanying drawings in which:

[0014]FIG. 1(a) is a plane view describing an evaluating patternaccording to a first preferred embodiment.

[0015]FIG. 1(b) is a cross section at a portion along line X-′X shown inFIG. 1(a).

[0016]FIG. 2(a) to FIG. 2(c) are cross sections describing processes forforming the evaluating pattern shown in FIG. 1.

[0017]FIG. 3(a) is a plane view describing an evaluating patternaccording to a second preferred embodiment.

[0018]FIG. 3(b) is a cross section at a portion along line X-′X shown inFIG. 3(a).

[0019]FIG. 4 is a plane view describing the evaluating pattern shown inFIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] The present invention will be described hereinafter withreference to the accompanying drawings. The drawings used for thisdescription typically illustrate major characteristic parts in orderthat the present invention will be easily understood.

[0021] A first preferred embodiment is described hereinafter referringto FIG. 1 and FIG. 2. FIG. 1(a) is a plane view describing an evaluatingpattern according to a first preferred embodiment. FIG. 1(b) is a crosssection at a portion along line X-′X shown in FIG. 1(a). FIG. 2(a) toFIG. 2(c) are cross sections describing processes for forming theevaluating pattern shown in FIG. 1.

[0022] The evaluating pattern is comprised of a rectangular conductivepattern 10, an intermediate insulating layer 20, a conductive material30 which is filled into contact holes formed in the insulating layer 20on the middle of the conductive pattern 10.

[0023] The evaluating pattern is located on grid lines GL whichpartition off a semiconductor wafer SUB into chip regions CR where aplurality of semiconductor chips are formed thereon. That is, the chipregions CR are respectively divided on the semiconductor wafer SUB bythe grid lines GL. If there is a space for the evaluating pattern in thechip regions CR, the evaluating pattern may be formed in the chip regionCR.

[0024] The conductive pattern 10 is a rectangular configuration which iscomprised of aluminum (Al). Naturally, other conductive materials can beapplied for the conductive pattern 10. The conductive pattern 10 isformed on the grid line GR while conductive lines are formed in the chipregions CR, as shown in FIG. 2(a).

[0025] The intermediate insulating layer 20 is comprised of silicondioxide (SiO2). The insulating layer 20 is not limited to a singlelayer, a multiple insulating layer can be used. For example, themultiple insulating layer is comprised of a silicon oxide layer whichincludes fluorine (SiOF) and a silicon dioxide layer (SiO2) which isformed on the silicon oxide layer which includes fluorine (SiOF). Theinsulating layer 20 is simultaneously formed on the chip regions CR andthe grid lines GR, as shown in FIG. 2(b).

[0026] The conductive material 30 is comprised of a refractory metal ora compound made up of the refractory metal and other material, such astungsten (W), titanium (Ti) and titanium-nitride (TiN). This conductivematerial 30 is filled into contact holes which are formed in theinsulating layer 20, as shown in FIG. 2(c).

[0027] An erosion which occurs in the evaluating pattern is equivalentto an erosion which occurs in a densely region in the chip region CR.That is, the evaluating pattern shows an erosion occurred in the denselyregion where many contact holes or conductive lines are thicken in annarrow distance in the chip region. Therefore, the erosion occurred inthe chip region CR can be evaluated by measuring the erosion in theevaluating pattern.

[0028] The erosion in the evaluating pattern can be measured by acontact type measure for measuring bumps occurred by the erosion. Forexample, the erosion is measured by scanning the measure along line X-X′shown in FIG. 1(b).

[0029] In this embodiment, the contact holes are located on the middleof the conductive pattern 30 at the density of 25%. Each distancebetween the neighboring contact holes is substantially equal. Thedensity can be designed by a designer corresponding to the density ofcontact holes or conductive lines in the chip regions. That is, thecontact holes in the evaluating patter are located according to thehighest density in the chip regions CR. As the conductive pattern 10 issimultaneously formed with the conductive patterns in the chip regionCR, a rectangular pattern which are similar to the conductive patternsin the chip region is suitable for the conductive pattern 10.

[0030] According to the first preferred embodiment, it is easy torecognize the evaluation pattern among many various patterns on asemiconductor wafer. As a measuring point is arranged in the middle ofthe rectangular conductive pattern, it is facile to identify themeasuring point. That is, the measuring point in the middle of therectangular conductive pattern is easily identified by recognizing sidesof the rectangular conductive pattern. Further, in the case where therectangular configuration of the conductive pattern is a square, asdistance between the middle of the conductive pattern and one side isequal, a measurement from any directions is allowable. Therefore, afacility of the measurement can be raised.

[0031] A second preferred embodiment is described hereinafter referringto FIG. 3 and FIG. 4. FIG. 3(a) is a plane view describing an evaluatingpattern according to a second preferred embodiment. FIG. 3(b) is a crosssection at a portion along line X-′X shown in FIG. 3(a). FIG. 4 is aplane view describing the evaluating pattern shown in FIG. 3. The sameelements mentioned above are marked at the same symbols and adescription thereof is omitted.

[0032] The evaluating pattern of this embodiment is comprised of arectangular conductive pattern 10, an intermediate insulating layer 20,a conductive material 30 which is filled into contact holes formed inthe insulating layer 20 on the middle of the conductive pattern 10. Inthis embodiment, an arrangement of the contact holes differs from thatof the first preferred embodiment.

[0033] That is, the conductive pattern 10 has a central region C, afirst region R1 which surrounds the central region C and a second regionR2 which surrounds the first region R2, as shown in FIG. 4. In thisembodiment, length of one side in the central region C is 50 μm, lengthof one side in the first region R1 is 100 μm and length of one side inthe second region R2 is 150 μm. These sizes are properly defined by adesigner. If the length in the central region is comparatively long asthis embodiment, a popular optical measure for measuring the erosion canbe used. However, if the length in the central region is short, that is,the central region becomes narrow, a sophisticated optical measure formeasuring the erosion is necessary to measure the erosion.

[0034] In this embodiment, the contact holes are formed in theinsulating layer 20 in the first region R1. The conductive material 30are filled into the holes. That is, the contact holes are not arrangedin the central region C. Also, the contact holes are not arranged in thesecond region R2. The erosion does not occur in the second region R2.The contact holes, that is the conductive material 30, are symmetricwith the central region C. Similar to the first embodiment, eachdistance between the neighboring contact holes is equal.

[0035] As the contact holes are not arranged in the central region C, itis difficult to arise an erosion therein, compared with the first regionR1. That is, some erosions may be occurred by the effect from thecontact holes in the first region R1. However, as a densely arrangementis not in the central region C, an excessive erosion does not occur inthe central region C.

[0036] Similarly, the evaluating pattern of this embodiment is locatedon the grid lines GL. Each element in this embodiment can be formed bythe processes described in the first preferred embodiment.

[0037] Similarly, an erosion which occurs in the evaluating pattern isequivalent to an erosion which occurs in a densely region in the chipregion CR. That is, the evaluating pattern shows an erosion occurred inthe densely region where many contact holes or conductive lines arethicken in narrow distance in the chip region. Therefore, the erosionoccurred in the chip region CR can be evaluated by measuring the erosionin the evaluating pattern.

[0038] In this embodiment, the erosion is evaluated by measuringthickness T20 of the insulating layer 20 in the second region R2andthickness α of the insulating layer 20 in the central region C, using anon-contact type optical measure. The optical measure can measurethickness of bumps occurred by the erosion without contacting. Thedifferential thickness β is counted by the thickness T20 and thethickness α. The erosion E2 is calculated by an interrelation betweenthe differential thickness β and the erosion E2. The interrelation isdefined by a designer in advance.

[0039] Similar to the first embodiment, directly measurement by thecontact type measure for measuring bumps occurred by the erosion can beapplied for this embodiment, an indirectly measurement is shown in thisembodiment without using the contact type measure.

[0040] The density of the contact holes in the first region R1 can bedesigned by a designer corresponding to the density of contact holes orconductive lines in the chip regions. That is, the contact holes in theevaluating patter are located according to the highest density in thechip regions CR. As the conductive pattern 10 is simultaneously formedwith the conductive patterns in the chip region CR, a rectangularpattern which are similar to the conductive patterns in the chip regionis suitable for the conductive pattern 10.

[0041] According to the second preferred embodiment, in addition to theeffect of the first preferred embodiment, an erosion occurred in thefirst region can be precisely measured by measuring thickness of theinsulating layer in the central region and the first region.

[0042] As the result, an evaluating pattern for measuring an erosion ofa semiconductor wafer polished by a chemical mechanical polishing can berealized without declining a yield of the semiconductor device.

[0043] The present invention has been described above with reference toillustrative embodiments. However, this description must not beconsidered to be confined only to the embodiments illustrated. Variousmodifications and changes of these illustrative embodiments and theother embodiments of the present invention will become apparent to oneskilled in the art from reference to the description of the presentinvention. It is therefore contemplated that the appended claims willcover any such modifications or embodiments as fall within the truescope of the invention.

What is claimed is:
 1. An evaluating pattern for measuring an erosion ofa semiconductor wafer which is polished by a chemical mechanicalpolishing method, comprising: a conductive pattern which has arectangular configuration; an insulating layer which is formed on theconductive pattern; and a conductive material filled into contact holeswhich is formed in the insulating layer on the middle of the conductivepattern.
 2. The evaluating pattern according to claim 1, whereindistances between the neighboring contact holes are equal.
 3. Theevaluating pattern according to claim 1, wherein the conductive patternis a square configuration.
 4. The evaluating pattern according to claim1, wherein the insulating layer is comprised of a first silicon oxidelayer and a second silicon oxide layer which is formed on the firstsilicon oxide layer, wherein the first silicon oxide layer includesfluorine and the second silicon oxide layer does not include fluorine.5. The evaluating pattern according to claim 1, wherein the evaluatingpattern is formed on a grid line which partitions off the semiconductorwafer into a plurality of semiconductor chips.
 6. An evaluating patternfor measuring an erosion of a semiconductor wafer which is polished by achemical mechanical polishing method, comprising: a rectangularconductive pattern which has a middle region, a first region whichsurrounds the middle region and a second region which surrounds thefirst region; an insulating layer which is formed on the first, secondand the middle region; and a conductive material filled into contactholes which is formed in the insulating layer on the second region. 7.The evaluating pattern according to claim 6, wherein the contact holesare symmetrical with the middle region.
 8. The evaluating patternaccording to claim 6, wherein an erosion on the first region is countedfrom thickness of the insulating layer on the middle region and thesecond region.